MIL-M-38510-176 Microcircuits, Digital, Cmos, Latches, Monolithic Silicon, Positive LogicThis specification covers the detail requirements for monolithic silicon, CMOS, logic microcircuits. Two product assurance classes and a choice of case outlines, lead finishes, and radiation hardness assurance RHA are provided and are reflected in the complete Part or Identifying Number PIN. For this product, the requirements of MIL-M-38510 have been superseded by MIL-PRF-38535 see 6.3.

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MIL-M-38510/176B

1/  Pins not designated may be "HIGH" level logic, "LOW" level logic or open.  Exceptions are as follows:  VIC(pos)  tests, the

VSS terminals shall be open;  VIC(neg) tests, the VDD  terminal shall be open;  ISS tests, the output terminals shall be open.

2/  The ISS measurements shall be performed in sequence.

3/  Clock device to time slot 26 of sequence B in 9/ before performing leakage test.

4/  The input/output conditions, contained in 9/ shall be used.  For device type 01, the timing sequence specified in 9/, sequence B, (except for the truth table test) shall be used; for device type 02, the timing sequence specified in 9/, sequence A shall be used.

5/  The device manufacturer may, at his option, measure IIL  and IIH  at 25°C for each individual input or measure all inputs together.

6/  See 4.4.1c.

7/  The truth table shall be performed using the input/output conditions and timing sequence contained in 9/, sequence C.

8/  Write disable (WD) must be held at logic "1" while changing the address lines (A0, A1, A2) to select the next output bit.

9/  The following timing sequence and input/output conditions shall apply:

Input/output conditions.

SEQUENCE A

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