MIL-M-38510-176 Microcircuits, Digital, Cmos, Latches, Monolithic Silicon, Positive LogicThis specification covers the detail requirements for monolithic silicon, CMOS, logic microcircuits. Two product assurance classes and a choice of case outlines, lead finishes, and radiation hardness assurance RHA are provided and are reflected in the complete Part or Identifying Number PIN. For this product, the requirements of MIL-M-38510 have been superseded by MIL-PRF-38535 see 6.3.

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MIL-M-38510/176B

TABLE I. Electrical performance characteristics - Continued.

Test	Symbol	Conditions -55°C = TA = +125°C Unless otherwise specified	Device type	Limits		Units
Test	Symbol	Conditions -55°C = TA = +125°C Unless otherwise specified	Device type	Min	Max	Units
Propagation delay times, STROBEm to Qnm, high to low level and low to high level	tPHL1, tPLH1	VDD = 5.0 Vdc, CL = 50 pF RL = 200 kO (see figure 4)	02	17	400	ns
Propagation delay times, Dnm to Qnm, high to low level and low to high level	tPHL2, tPLH2	VDD = 5.0 Vdc, CL = 50 pF RL = 200 kO (see figure 4)	02	14	400	ns
Propagation delay times, RESETm to Qnm, high to low level and low to high level	tPHL3, tPLH3	VDD = 5.0 Vdc, CL = 50 pF RL = 200 kO (see figure 4)	02	13	378	ns
Propagation delay times, STROBEm to Qnm, high to low level and low to high level	tPHL1, tPLH1	VDD = 10.0 Vdc, CL = 50 pF RL = 200 kO (see figure 4) TA = 25°C	02	7	140	ns
Propagation delay times, Dnm in to Qnm, high to low level and low to high level	tPHL2, tPLH2	VDD = 10.0 Vdc, CL = 50 pF RL = 200 kO (see figure 4) TA = 25°C	02	6	120	ns
Propagation delay times, RESETm to Qnm, high to low level and low to high level	tPHL3, tPLH3	VDD = 10.0 Vdc, CL = 50 pF RL = 200 kO (see figure 4) TA = 25°C	02	5	100	ns
Three-state output propagation OUTPUT DISABLEm delay times, output high to high impedance, output low to high impedance, high impedance to output low, high impedance to output high	tPHZ	VDD = 5.0 Vdc, CL = 50 pF RL = 200 kO (see figure 4)	02	11	310	ns
	tPLZ		02	9	255
	tPZL		02	9	255
	tPZH		02	10	275
Three-state output propagation OUTPUT DISABLEm delay times, output high to high impedance, output low to high impedance, high impedance to output low, high impedance to output high	tPHZ	VDD = 10.0 Vdc, CL = 50 pF RL = 200 kO (see figure 4)	02	6	120	ns
	tPLZ		02	5	100
	tPZL		02	5	100
	tPZH		02	5	100
Minimum RESETm pulse width	tPR	VDD = 5.0 Vdc, CL = 50 pF RL = 200 kO (see figure 4)	02		280	ns
Minimum STROBEm pulse width	tPST		02		200	ns
Minimum data setup time, low to high level	tSLH		02		70	ns
Minimum data hold time, high to low level	tHHL		02		0	ns