MIL-M-38510-763 Microcircuits, Digital, Advanced Cmos, Counters, Monolithic Silicon, Positive LogicThis specification covers the detail requirements for monolithic silicon, advanced CMOS, logic microcircuits. Two product assurance classes and a choice of case outlines, lead finishes, and radiation hardness assurance RHA are provided and are reflected in the complete Part or Identifying Number PIN. For this product, the requirements of MIL-M-38510 have been superseded by MIL-PRF-38535 see 6.3.

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MIL-M-38510/7638

TA8LE I. Electrical performance characteristics - Continued.

Test and MIL-STD-883 test method	Symbol	Test conditions 1/ -55°C ≤ TC ≤ +125°C 3.0 V ≤ VCC ≤ 5.5 V unless otherwise specified		Device type 2/	VCC	Group A subgroups	Limits 1/		Unit
							Min	Max
Propagation delay time, U/D to RC 3003	tPHL8, tPLH8 4/ 5/ 13/ 14/	CL = 50 pF RL = 500 O		05	3.0 V	9,11	1.0	12.5	ns
						10	1.0	15.0
		See figures 5 and 6	M	05		9	1.0	12.5
			D	05			1.0	12.5
			P,L,R	05			1.0	12.5
		CL = 50 pF RL = 500 O		05	4.5 V	9,11	1.0	9.0	ns
						10	1.0	11.0
		See figures 5 and 6	M	05		9	1.0	9.0
			D	05			1.0	9.0
			P,L,R	05			1.0	9.0
Propagation delay time, U/D to TC 3003	tPHL9, tPLH9 4/ 5/ 13/ 14/	CL = 50 pF RL = 500 O		05	3.0 V	9,11	1.0	11.0	ns
						10	1.0	14.0
		See figures 5 and 6	M	05		9	1.0	11.0
			D	05			1.0	11.0
			P,L,R	05			1.0	11.0
		CL = 50 pF RL = 500 O		05	4.5 V	9,11	1.0	8.5	ns
						10	1.0	10.5
		See figures 5 and 6	M	05		9	1.0	8.5
			D	05			1.0	8.5
			P,L,R	05			1.0	8.5
Propagation delay time, Pn to Qn 3003	tPHL10, tPLH10 4/ 5/ 13/ 14/	CL = 50 pF RL = 500 O		05	3.0 V	9,11	1.0	13.5	ns
						10	1.0	16.5
		See figures 5 and 6	M	05		9	1.0	13.5
			D	05			1.0	13.5
			P,L,R	05			1.0	13.5
		CL = 50 pF RL = 500 O		05	4.5 V	9,11	1.0	9.0	ns
						10	1.0	11.5
		See figures 5 and 6	M	05		9	1.0	9.0
			D	05			1.0	9.0
			P,L,R	05			1.0	9.0
Propagation delay time, PL to Qn 3003	tPHL11, tPLH11 4/ 5/ 13/ 14/	CL = 50 pF RL = 500 O		05	3.0 V	9,11	1.0	14.0	ns
						10	1.0	18.0
		See figures 5 and 6	M	05		9	1.0	14.0
			D	05			1.0	14.0
			P,L,R	05			1.0	14.0
		CL = 50 pF RL = 500 O		05	4.5 V	9,11	1.0	10.0	ns
						10	1.0	12.5
		See figures 5 and 6	M	05		9	1.0	10.0
			D	05			1.0	10.0
			P,L,R	05			1.0	10.0

1/ Each input/output, as applicable, shall be tested at the specified temperature for the specified limits. Output terminals not designated shall be high level logic, low level logic, or open, except as follows:

a. VIC (pos) tests, the GND terminal can be open. TC = +25°C. b. VIC (neg) tests, the VCC terminal shall be open. TC = +25°C.

c. All ICC tests, the output terminal shall be open. When performing these tests, the current meter shall be

placed in the circuit such that all current flows through the meter.

For negative and positive voltage and current values, the sign designates the potential difference in reference to GND and the direction of current flow, respectively; and the absolute value of the magnitude, not the sign, is relative to the minimum and maximum limits, as applicable, listed herein.