MIL-M-38510-59 Microcircuits, Digital, Cmos, Decoder, Monolithic Silicon, Positive LogicThis specification covers the detail requirements for monolithic silicon, CMOS logic microcircuits. Two product assurance classes and a choice of case outlines , lead finishes, and radiation hardness assurance RHA are provided and are reflected in the complete Part or Identifying Number PIN. For this product the requirements of MIL-M-38510 have been superseded by MIL-PRF-38535 see 6.3.

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MIL-M-38510159D

TABLE III. Group A inspection for device type 51 - Continued.

11 Pins not designated may be "high" level logic, "low level logic, or open. Exceptions are as follows: For VIC(POS) tests, the VSS terminal shall be open; for VIC(NEG) tests, the VDD terminal shall be open; for ISS tests, the output terminals shall be open.

21 The ISS tests shall be performed in sequence.

31 The following sequence and input1output conditions shall apply:

Test

VDD

Input levels

Output levels

VIH1

VIL1

5.0 V

VDD

3.5 V

1.5 V

VSS

4.5 V

Min

0.5 V

Max

VIH2

VIL2

10.0 V

VDD

7.0 V

3.0 v

VSS

9.0 V

Min

1.0 V

Max

VIH3

VIL3

15.0 V

VDD

11.0 V

4.0 V

VSS

13.5 V

Min

1.5 V

Max

Input1output conditions

Truth table

41 The device manufacturer may, at his option, measure IIL and IIH at 25°C for each individual input or measure all inputs together.

51 See 4.4.1c.

61 The truth table tests shall be performed in sequence.

71 the truth table tests shall be performed at VIH and VDD s 5 Vdc and � 18 Vdc. L = VSS +0.50 V maximum, and H = VDD -0.50 Vdc minimum.

81 Input conditions A, B, and C refer to waveforms of figure 4.