MIL-M-38510/371B
NOTES:
1. Clock input pulse characteristics: t1 = t0 = 6 ±1.5 ns; tp (clock) = 16.5 ns; PRR ≤ 1 MHz.
2. D input pulse characteristics: t1 = t0 = 6 ±1.5; tsetup = 15 ns; thold = 2 ns; tp = 17 ns; PRR is 50% on the clock PRR.
3. For fMAX, the clock input pulse characteristics are as follows:
t1 = t0 ≤ 3 ns; tp (clock) = 16.5 ns; PRR = 30 MHz.
The D input pulse shall be one-half of the frequency of the clock and the D ↑ and ↓
shall be coincident with the clock ↓. t1 = t0 = 6 ±1.5 ns.
4. CL = 50 pF ±10% (including jig and probe capacitance without package in test fixture).
5. RL = 499ν ±1%.
6. Voltage measurements are to be made with respect to network ground terminal.
FIGURE 4. Synchronous switching test circuit (high-level data) device type 01.
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