MIL-M-38510/28C
TABLE I. Electrical performance characteristics - Continued
Test |
Symbol |
Conditions |
Device type |
Limits |
Units |
|
Min |
Max |
|||||
Width of clock pulse |
tP1 |
VCC = 5 V, CL = 50 pF, RL = 1600 0 (figure 6) |
03 |
65 |
20 |
ns |
Width of MR pulse with clock HIGH |
tP2 |
65 |
20 |
ns |
||
Width of MR pulse with clock LOW |
tP3 |
75 |
20 |
ns |
||
Shift Right frequency |
fSR |
VCC = 5 V, CL = 50 pF, RL = 1600 0 (figure 7) |
04 |
5 |
25 |
MHz |
Propagation delay, low-to- high, clock to output |
tPLH1 |
14 |
100 |
ns |
||
Propagation delay, high-to- low, clock to output |
tPHL1 |
20 |
100 |
ns |
||
Propagation delay, high-to- low, MR to output (except Q3 ) |
tPHL2 |
20 |
100 |
ns |
||
Propagation delay, high-to- low, MR to Q3 |
tPHL3 |
25 |
120 |
ns |
||
Clock pulse width |
tP1 |
20 |
55 |
ns |
||
Master reset pulse width |
tP2 |
20 |
75 |
ns |
||
Setup time, data to clock |
tSETUP1 |
25 |
60 |
ns |
||
Setup time, PE to clock |
tSETUP2 |
25 |
70 |
ns |
||
Hold time, data to clock |
tHOLD1 |
-40 |
0 |
ns |
||
Hold time, PE to clock |
tHOLD2 |
-65 |
-20 |
ns |
||
Recovery time, MR to clock |
tREC |
20 |
60 |
ns |
||
Maximum clock frequency |
fMAX |
VCC = 5 V, CL = 50 pF, RL = 3.9 k0 (figure 8) |
05 |
3 |
--- |
MHz |
Propagation delay time, high-to-low level, clear input to Q outputs |
tPHL1 |
140 |
ns |
|||
Propagation delay time, high-to-low level, clock input to Q outputs |
tPHL2 |
135 |
ns |
|||
Propagation delay time, low-to-high level, clock input to Q outputs |
tPLH2 |
120 |
ns |
|||
Width of clock or clear pulse |
tP |
60 |
--- |
ns |
||
Data setup time |
tSETUP(H) tSETUP(L) |
40 40 |
--- --- |
ns ns |
||
Data hold time |
tHOLD(H) tHOLD(L) |
-20 -20 |
--- --- |
ns ns |
||
1/ Not more than one output should be shorted at a time.
2/ ICC is measured in accordance with Table III requirements.
7
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