MIL-M-38510-28 Microcircuits, Digital, Ttl, Low Power Shift Registers, Monolithic SiliconThis specification covers the detail requirements for monolithic, silicon, TTL, low power shift register, microcircuits. Two product assurance classes and a choice of case outlines and lead finishes are provided for each type and are reflected in the complete part number. For this product, the requirements of MIL-M-38510 have been superseded by MIL-PRF-38535, see 6.4.

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MIL-M-38510/28C

TABLE I. Electrical performance characteristics - Continued

Test	Symbol	Conditions	Device type	Limits		Units
Test	Symbol	Conditions	Device type	Min	Max	Units
Maximum shift frequency	fMAX	VCC = 5 V, CL = 50 pF, RL = 4 k0 (see figure 4)	01	3	---	MHz
Propagation delay time, low-to-high level from clock 1 or clock 2 to outputs	tPLH				250	ns
Propagation delay time, high-to-low level from clock 1 or clock 2 to outputs	tPHL				250	ns
Low level setup time at mode control with respect to clock 1 input	t1			225	---	ns
High level setup time at mode control with respect to clock 2 input	t2			200	---	ns
Low level setup time at mode control with respect to clock 2 input	t3			0	---	ns
High level setup time at mode control with respect to clock 1 input	t4			100	---	ns
Width of clock pulse	tP	See figure 4	01	200	---	ns
Setup time required at serial A, B, C, D inputs	tSETUP(H) tSETUP(L)	See figure 4	01	100 100	--- ---	ns ns
Hold time required at serial A, B, C, D inputs	tHOLD(H) tHOLD(L)	See figure 4	01	0 0	--- ---	ns ns
Maximum clock frequency	fMAX	VCC = 5 V, CL = 50 pF, RL = 800 0 (figure 5)	02	12	---	MHz
Propagation delay time, high-to-low level, clear input to Q outputs	tPHL1			10	110	ns
Propagation delay time, high-to-low level, clock input to Q outputs	tPHL2			10	100	ns
Propagation delay time, low-to-high level, clock input to Q outputs	tPLH2			10	80	ns
Width of clock or clear pulse	tP			40	---	ns
Data setup time	tSETUP(H) tSETUP(L)			30 30	--- ---	ns ns
Data hold time	tHOLD(H) tHOLD(L)			0 0		ns ns
Maximum clock frequency	fMAX	VCC = 5 V, CL = 50 pF, RL = 1600 0 (figure 6)	03	6	---	MHz
Propagation delay time, low-to-high level, clock input to Q outputs	tPLH1			11	55	ns
Propagation delay time, high-to-low level, clock input to Q outputs	tPHL1			20	100	ns
Propagation delay, high-to- low level, MR to Q outputs	tPHL2			30	125	ns

See footnotes at end of table.