MIL-M-38510-203 Microcircuits, Digital, 1024 Bit Schottky, Bipolar, Programmable Read-Only Memory Prom, Monolithic SiliconThis specification covers the detail requirements for monolithic silicon, programmable read-only memory PROM microcircuits which employ thin film nichrome NiCr resistors, tungsten W, titanium tungsten TiW, or zapped vertical emitter ZVE as the fusible link or programming element. Two product assurance classes and a choice of case outlines and lead finishes are provided and are reflected in the complete part number. For this product, the requirements of MIL-M-38510 have been superseded by MIL-PRF-38535, see 6.4.

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MIL-M-38510/203E

TABLE I. Electrical performance characteristics.

Characteristic	Symbol	Conditions 1/ -55°C ≤ TC ≤ +125°C	Device type	Limits		Unit
Characteristic	Symbol	Conditions 1/ -55°C ≤ TC ≤ +125°C	Device type	Min	Max	Unit
High level output voltage	VOH	VCC = 4.5 V; IOH = -2 mA, VIL = 0.8 V, VIH = 2.0 V	02,04	2.4	---	V
Low level output voltage	VOL	VCC = 4.5 V; IOL = 16 mA 2/ VIL = 0.8 V, VIH = 2.0 V	01,02 03,04	---	0.5	V
Input clamp voltage	VIC	VCC = 4.5 V; IIN = -10 mA; TC = 25°C	01,02 03,04	---	-1.5	V
Maximum collector cut-off current	ICEX	VCC = 5.5 V; VO = 5.2 V	01,03	---	100	µA
High impedance (off-state) output high current	IOHZ	VCC = 5.5 V; VO = 5.2 V	02,04	---	100	µA
High impedance (off-state) output low current	IOLZ	VCC = 5.5 V; VO = .5 V	02,04	---	-100	µA
High level input current	IIH1	VCC = 5.5 V; VIN = 5.5 V	01,02 03,04	---	50	µA
High level input current	IIH2	VCC = 5.5 V; VIN = 4.5 V; special program pin	01,02 03,04	---	100	µA
Low level input current	IIL	VCC = 5.5 V; VIN = 0.5 V	01,02 03,04	-1	-250	µA
Short circuit output current	IOS	VCC = 5.5 V; 3/ VO = 0.0 V	02,04	-10	-100	mA
Supply current	ICC	VCC = 5.5 V; VIN = 0; outputs open	01,02 03,04	---	130	mA
Propagation delay time high-to-low level logic, address to output	tPHL1	VCC = 4.5 V and 5.5 V; CL = 30 pF minimum; see figure 5	01, 02	---	75	ns
	tPHL1		03, 04	---	35	ns
Propagation delay time low-to-high level logic, address to output	tPLH1		01, 02	---	75	ns
	tPLH1		03, 04	---	35	ns
Propagation delay time high-to-low level logic, enable to output	tPHL2		01, 02	---	35	ns
	tPHL2		03, 04	---	20	ns
Propagation delay time low-to-high level logic, enable to output	tPLH2		01, 02	---	35	ns
	tPLH2		03, 04	---	20	ns

1/ Complete terminal conditions shall be specified in table III.

2/ IOL = 12 mA for circuit B.

3/ Not more than one output shall be grounded at one time. Output shall be at high logic level prior to test.