MIL-M-38510-174 Microcircuits, Digital, CMOS, Inverter, NAND Buffer Driver, Strobed Hex Inverter/Buffer, Voltage Level Shifter, Monolithic Silicon, Positive LogicThis specification covers the detail requirements for monolithic silicon, CMOS, logic microcircuits. Two product assurance classes and a choice of case outlines, lead finishes, and radiation hardness assurance RHA are provided and are reflected in the complete Part or Identifying Number PIN. For this product, the requirements of MIL-M-38510 have been superseded by MIL-PRF-38535 see 6.3.

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MIL-M-38510/1748

TA8LE I. Electrical performance characteristics - Continued.

Test	Symbol	Conditions 1/ VSS = 0 V -55°C = TA = +125°C Unless otherwise specified	Device type	Limits		Unit
Test	Symbol		Device type	Min	Max	Unit
Propagation delay time, high-to-low level	tPHL	VDD = 10.0 V, CL = 50 pF RL = 200 kO. See figure 4 For group A requirements TA = 25°C VCC = 5.0 V for device type 04.	01	3	60	ns
			02	5	90
			03	6	120
			04	30	840
Propagation delay time, low-to-high level	tPLH		01	3	60
			02	6	120
			03	9	180
			04	13	365
Three-state disable delay time, output high to high impedance	tPHZ	VDD = 5.0 V, CL = 50 pF RL = 1.0 kO (see figure 4)	03,04	6	170	ns
Three-state disable delay time, high impedance to output high	tPZH		03	11	310
	tPZH		04	32	895
Three-state disable delay time, output low to high impedance	tPLZ		03	13	350
	tPLZ		04	37	1040
Three-state disable delay time, high impedance to output low	tPZL		03	13	350
	tPZL		04	10	280
Three-state disable delay time, output high to high impedance	tPHZ	VDD = 10.0 V CL = 50 pF RL = 1.0 kO For group A requirements TA = 25°C See figure 4 VCC = 5.0 V for device type 04	03	4	80	ns
	tPHZ		04	6	170
Three-state disable delay time, high impedance to output high	tPZH		03	5	100
	tPZH		04	32	895
Three-state disable delay time, output low to high impedance	tPLZ		03	7	130
	tPLZ		04	37	1040
Three-state disable delay time, high impedance to output low	tPZL		03	6	110
	tPZL		04	10	280
Transition time, high-to-low, low-to-high level	tTHL, tTLH	VDD = 5.0 V, CL = 50 pF RL = 200 kO (see figure 4)	01	10	280	ns
	tTHL		03	6	170
	tTLH		03	10	280
	tTHL, tTLH		04	5	140
Transition time, high-to-low level	tTHL	VDD = 10.0 V, CL = 50 pF RL = 200 kO. See figure 4 For group A requirements TA = 25°C VCC = 5.0 V for device type 04	01	5	100	ns
			02	2	40
			03	3	60
			04	5	140
Transition time, low-to-high level	tTLH		01	5	100
			02	4	70
			03	5	100
			04	5	140

1/ Complete terminal conditions shall be as specified in table III.

2/ Input current at one input mode.