MIL-M-38510-119 Microcircuits, Linear, Low Power, Low Noise, Bi-Fet Operational Amplifiers, Monolithic SiliconThis specification covers the detail requirements for monolithic silicon, BI-FET operational amplifiers. Two product assurance classes and a choice of case outlines and lead finishes are provided and are reflected in the complete part number. For this product, the requirements of MIL-M-38510 have been superseded by MIL-PRF-38535, see 6.3.

Pages 1 - 2 - 3 - 4 - 5 - 6 - 7 - 8 - 9 - 10 - 11 - 12 - 13 - 14 - 15 - 16 - 17 - 18 - 19 - 20 - 21 - 22 - 23 - 24 - 25

Characteristics

Symbol

Conditions   1/

±VCC = ±15 V (see 3.4 and figure 3

unless otherwise specified)

Device type

Limits

Units

Min

Max

Input offset voltage

VIO

±VCC = ±5V at

VCM = 0 V, and

±VCC = ±15 V at

VCM = ±11 V, 0 V

TA = +25°C

All

-5

5

mV

-55°C s TA s +125°C

-7

7

Input offset voltage temperature sensitivity

�VIO/

�T

VCM = 0 V

All

-30

30

µV/°C

Input offset current

IIO  2/

VCM = 0 V, t s 25 ms, TJ = +25°C

All

-100

100

pA

VCM = 0 V, t s 25 ms, TJ = +125°C

-20

20

nA

Input bias current

3/ 4/

+IIB, -IIB

VCC = ±15 V, VCM = +11 V, t s 25 ms, TJ = +25°C

All

-200

1,200

pA

VCC = ±15 V, VCM = +11 V, t s 25 ms, TJ = +125°C

-10

70

nA

±VCC = ±15 V, VCM = 0 V, t s 25 ms, TJ = +25°C

All

-200

200

pA

±VCC = ±15 V, VCM = 0 V, t s 25 ms

TJ = +125°C

-10

50

nA

±VCC = ±15 V, VCM = -11 V, t s 25 ms, TJ = +25°C

All

-400

200

pA

±VCC = ±15 V, VCM = -11 V, t s 25 ms, TJ = +125°C

-10

50

nA

Power supply rejection ration

+PSRR

+VCC = 20 V, 10 V; -VCC = -15 V

All

80

dB

-PSRR

+VCC = 15 V; -VCC = -20 V, -10 V

80

Input voltage        5/ common mode rejection

CMR

-11 V s VCM s 11 V

All

80

dB

Adjustment for     6/

input offset voltage

VIO (ADJ+)

VCM = 0 V

01, 02

04, 05

+8

mV

VIO (ADJ-)

VCM = 0 V

-8

Output short          7/

circuit current

(for positive output)

IOS(+)

t s 25 ms (short circuit to ground)

01, 02,

03

-40

mA

04, 05,

06

-80