MIL-M-38510-765 Microcircuits, Digital, Advanced Cmos, Shift Registers, Monolithic Silicon, Positive LogicThis specification covers the detail requirements for monolithic silicon, advanced CMOS, logic microcircuits. Two product assurance classes and a choice of case outlines, lead finishes, and radiation hardness assurance RHA are provided and are reflected in the complete Part or Identifying Number PIN. For this product, the requirements of MIL-M-38510 have been superseded by MIL-PRF-38535 see 6.3.

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MIL-M-3851O/765A

Device type O6

Asynchronous operations (CP, DSO, DS7 = x; OE1, OE2 = L, SO and S1 shall not simultaneously = H).

Mode	Inputs			Inputs/outputs				Outputs
Mode	MR	SO	S1	I/OO	I/O1	- - -	I/O7	QO	Q7
Reset	L	x	x	L	L	- - -	L	L	L
Hold	H	L	L	N/C	N/C	- - -	N/C	N/C	N/C

Synchronous operations (MR = H, OE1, OE2 = L)

Mode	Inputs					Inputs/outputs 1/ 2/				Outputs 2/
Mode	CP	SO	S1	DSO	DS7	I/OO	I/O1	- - -	I/O7	QO	Q7
Load	t	H	H	x	x	z	z	- - -	z	DO	D7
Shift right	t	L	H	L	x	L	DO	- - -	D6	L	D6
Shift right	t	L	H	H	x	H	DO	- - -	D6	H	D6
Shift left	t	H	L	x	L	D1	D2	- - -	L	D1	L
Shift left	t	H	L	x	H	D1	D2	- - -	H	D1	H

1/ When SO = S1 = H simultaneously, outputs I/On are in a high impedance state (z).

2/ Shown are the state of the outputs after the low-to-high clock transition. DO to D7 represent the data that was stored in the eight flip-flops, QO to Q7, prior to the clock transition.

High z conditions

Mode	Inputs		Inputs/outputs 1/				Outputs
Mode	OE1	OE2	I/OO	I/O1	- - -	I/O7	QO	Q7
High z	H	x	z	z	- - -	z	2/	2/
High z	x	H	z	z	- - -	z	2/	2/

1/ When SO = S1 = H simultaneously, outputs I/On are in a high impedance state (z).

2/ During the high z condition, shift, hold, load, and reset operations can still occur.

Outputs QO and Q7 are affected accordingly.

H = High voltage level L = Low voltage level x = Irrelevant

z = High impedance

t = Low-to-high clock transition

N/C = No change

FIGURE 2. Truth tables.