MIL-M-38510-765 Microcircuits, Digital, Advanced Cmos, Shift Registers, Monolithic Silicon, Positive LogicThis specification covers the detail requirements for monolithic silicon, advanced CMOS, logic microcircuits. Two product assurance classes and a choice of case outlines, lead finishes, and radiation hardness assurance RHA are provided and are reflected in the complete Part or Identifying Number PIN. For this product, the requirements of MIL-M-38510 have been superseded by MIL-PRF-38535 see 6.3.

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MIL-M-38510/765A

TABLE I. Electrical performance characteristics and postirradiation end-point electrical parameter limits - Continued.

Test	Symbol	Test conditions, unless otherwise specified 1/		Device type 2/	VCC	Group A subgroups (test method)	-55°C/+25°C limits		+125°C limits		Unit
Test	Symbol	Test conditions, unless otherwise specified 1/		Device type 2/	VCC	Group A subgroups (test method)	Min	Max	Min 3/	Max 3/	Unit
Output enable time, S0 = S1 = H to I/On	tPZH2, tPZL2	CL = 50 pF RL = 5000		All	3.0 V	9,10,11 (3003)	1.0	19.5	1.0	23.5	ns
		See figure 3 4/ 14/	M,D,P, L,R 5/	06	3.0 V	9 (3003)	1.0	19.5			ns
		CL = 50 pF RL = 5000		All	4.5 V	9,10,11 (3003)	1.0	13.0	1.0	16.0	ns
		See figure 3 4/ 14/	M,D,P, L,R 5/	06	4.5 V	9 (3003)	1.0	13.0			ns
Output disable time,OEn to I/On	tPHZ1, tPLZ1	CL = 50 pF RL = 5000		All	3.0 V	9,10,11 (3003)	1.0	19.0	1.0	22.5	ns
		See figure 3 13/ 14/	M,D,P, L,R 5/	06	3.0 V	9 (3003)	1.0	19.0			ns
		CL = 50 pF RL = 5000		All	4.5 V	9,10,11 (3003)	1.0	14.0	1.0	17.0	ns
		See figure 3 13/ 14/	M,D,P, L,R 5/	06	4.5 V	9 (3003)	1.0	14.0			ns
Output disable time, S0 = S1 = H to I/On	tPHZ2, tPLZ2	CL = 50 pF RL = 5000		All	3.0 V	9,10,11 (3003)	1.0	19.0	1.0	22.5	ns
		See figure 3 4/ 14/	M,D,P, L,R 5/	06	3.0 V	9 (3003)	1.0	19.0			ns
		CL = 50 pF RL = 5000		All	4.5 V	9,10,11 (3003)	1.0	14.0	1.0	17.0	ns
		See figure 3 4/ 14/	M,D,P, L,R 5/	06	4.5 V	9 (3003)	1.0	14.0			ns

1/ Each input/output, as applicable, shall be tested at the specified temperature for the specified limits. Output terminals not designated shall be high level logic, low level logic, or open, except as follows:

a. VIC (pos) tests, the GND terminal can be open. TC = +25°C. b. VIC (neg) tests, the VCC terminal shall be open. TC = +25°C.

c. All ICC tests, the output terminal shall be open. When performing these tests, the current meter shall be

placed in the circuit such that all current flows through the meter.

2/ The word "All" in the device type column means non-RHA limits for all devices types. M, D, P, L, and R in the conditions column specify the postirradiation limits for those device types specified in the device type column.

3/ RHA samples do not have to be tested at TA = +125°C prior to irradiation.