MIL-M-38510-50 Microcircuits, Digital, Cmos, Nand Gates, Monolithic Silicon, Positive LogicThis specification covers the detail requirements for monolithic silicon, CMOS, logic microcircuits. Two product assurance classes and a choice of case outlines, lead finishes, and radiation hardness assurance RHA are provided and are reflected in the complete Part or Identifying Number PIN. For this product, the requirements of MIL-M-38510 have been superseded by MIL-PRF-38535 see 6.3.

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MIL-M-38510/50F

TABLE I. Electrical performance characteristics - Continued.

Test	Symbol	Conditions 1/ VSS = 0 V -55°C ≤ TA ≤ +125°C Unless otherwise specified		Device type	Limits		Unit
					Min	Max
Output low (sink) current	IOL1	VDD = 5 V dc VIN = 5.0 V VOL = 0.4 V dc		51, 52, 53	0.36		mA dc
	IOL2	VDD = 15 V dc VIN = 15 V VOL = 1.5 V dc		51, 52, 53	2.4		mA dc
Output high (source) current	IOH1	VDD = 5 V dc Any one input = VSS All other inputs = VDD VOH = 4.6 V dc		51, 52, 53	-0.36		mA dc
	IOH2	VDD = 15 V dc Any one input = VSS All other inputs = VDD VOH = 13.5 V dc		51, 52, 53	-2.4		mA dc
Input leakage current, high	IIH 2/	Measure inputs sequentially	VDD = 15 V dc	01, 02, 03		100.0	nA
			VDD = 18 V dc	51, 52, 53
Input leakage current, low	IIL 2/	Measure inputs sequentially	VDD = 15 V dc	01, 02, 03		-100.0	nA
			VDD = 18 V dc	51, 52, 53
Input capacitance	Ci	VDD = 0 V dc, f = 1 MHz, TA = 25°C		All		12	pF
Propagation delay time, high to low level	tPHL	VDD = 5 V dc, CL = 50 pF RL = 200 kO (See figure 3)		01	13	300	ns
				02	13	490
				03	13	265
				51	13	300
				52	13	490
				53	13	265
Propagation delay time, low to high level	tPLH			01, 03	13	225	ns
				02	13	375
				51, 53	13	225
				52	13	375
Transition time, high to low level	tTHL	VDD = 5 V dc, CL = 50 pF RL = 200 kO (See figure 3)		01	10	450	ns
				02	10	825
				03	10	375
				51	10	450
				52	10	825
				53	10	375

See footnotes at end of the table.