MIL-M-38510/21F
Device type 01 Positive logic: Low input to preset sets Q to high level
Low input to clear sets Q to low level
Preset and clear are independent of clock
NOTE8:
1. J = J1 J2 J3
2. K = K1 K2 K3
3. tn = Bit time before clock pulse.
4. tn+1 = Bit time after clock pulse.
Device type 02 Positive logic: Low input to preset sets Q to high level
Low input to clear sets Q to low level
Preset and clear are independent of clock
NOTE8:
1. R = R1 R2 R3
2. 8 = 81 82 83
3. tn = Bit time before clock pulse.
4. tn+1 = Bit time after clock pulse.
Description for device types 01 and 02
These flip-flops are based on the master slave principle and each has AND gate inputs for entry into the master section which are controlled by the clock pulse. The clock pulse also regulates the state of the coupling transistors which connect the master and slave sections. The sequence of operation as controlled by the clock pulse is as follows:
1. Isolate slave from master.
2. Enter information from AND gate inputs to master.
3. Disable AND gate inputs.
4. Transfer information from master to slave.
Figure 2. Truth tables and device descriptions.
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