MIL-M-38510-172 Microcircuits, Digital, Cmos, And-Or-Invert, Exclusive-Or, Exclusive-Nor Gates, Monolithic Silicon, Positive LogicThis specification covers the detail requirements for monolithic silicon, CMOS, logic microcircuits. Two product assurance classes and a choice of case outlines, lead finishes, and radiation hardness assurance RHA are provided and are reflected in the complete Part or Identifying Number PIN. For this product, the requirements of MIL-M-38510 have been superseded by MIL-PRF-38535 see 6.3.

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MIL-M-38510/172C

TABLE I. Electrical performance characteristics - Continued.

Test	Symbol	Conditions VSS = 0 V -55°C = TA = +125°C Unless otherwise specified	Device type	Limits		Unit
Test	Symbol		Device type	Min	Max	Unit
Input leakage 1/ current, high	IIH	VDD = 18 V dc Measure inputs sequentially; connect all unused inputs to VSS	01, 02, 04		45	nA
Input leakage 1/ current, high	IIH		03		100	nA
Input leakage 1/ current, low	IIL	VDD = 18 V dc Measure inputs sequentially; connect all unused inputs to VDD	01, 02, 04		-45	nA
Input leakage 1/ current, low	IIL		03		-100	nA
Input capacitance	Ci	VDD = 0 V dc, f = 1 MHz, TA = 25°C	All		7.5	pF
Propagation delay times, high to low level	tPHL	VDD = 5 V dc, CL = 50 pF RL = 200 kO (See figure 3)	01, 02	15	630	ns
		VDD = 5 V dc, CL = 50 pF RL = 200 kO (See figure 3)	03, 04	13	350	ns
		VDD = 10 V dc, CL = 50 pF RL = 200 kO, TA = 25°C (See figure 3)	01, 02	6	180	ns
			03, 04	6	120	ns
Propagation delay times, low to high level	tPLH	VDD = 5 V dc, CL = 50 pF RL = 200 kO (See figure 3)	01	25	870	ns
			02	25	980
			03, 04	13	350
		VDD = 10 V dc, CL = 50 pF RL = 200 kO, TA = 25°C (See figure 3)	01	10	250	ns
			02	14	280
			03, 04	6	120
Transition times, high to low level	tTHL	VDD = 5 V dc, CL = 50 pF RL = 200 kO (See figure 3)	All	10	280	ns
Transition times, high to low level	tTHL	VDD = 10 V dc, CL = 50 pF RL = 200 kO TA = +25°C (See figure 3)	All	5	100	ns
Transition times, low to high level	tTLH	VDD = 5 V dc, CL = 50 pF RL = 200 kO (See figure 3)	All	10	280	ns
Transition times, low to high level	tTLH	VDD = 10 V dc, CL = 50 pF RL = 200 kO TA = +25°C (See figure 3)	All	5	100	ns

1/ Input current of one input node.