MIL-M-38510-114 Microcircuits, Linear, Bi-Fet Operational Amplifiers, Monolithic SiliconThis specification covers the detail requirements for monolithic silicon, BI-FET operational amplifier microcircuit. Two product assurance classes and a choice of case outlines and lead finishes are provided and are reflected in the complete part number. For this product, the requirements of MIL-M-38510 have been superseded by MIL-PRF-38535, see 6.3.

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Test

Symbol

Conditions

-55°C σ TA σ +125°C

unless otherwise specified

See figure 3

Group A

subgroups

Device type

Limits

Unit

Min

Max

Input offset voltage

VIO

±VCC = ±5 V, VCM = 0 V

1

01,02,

03

-5

5

mV

04,05,

06

-2

2

±VCC = ±20 V,

VCM = ±15 V, 0 V

2,3

01,02,

03

-7

7

04,05,

06

-2.5

2.5

Input offset voltage

temperature sensitivity

VIO /

T

±VCC = ±20 V, VCM = 0 V

1,2,3

01,02,

03

-30

30

∝V/°C

04,05,

06

-10

10

Input offset current

IIO

±VCC = ±20 V, VCM = 0 V

TJ = +25°C

All

-20

20

pA

TJ =

+125°C

-20

20

nA

Input bias current     1/ 2/

+IIB

±VCC = ±20 V,

VCM = +15 V, t σ 25 ms

TJ = +25°C

All

-100

3500

pA

TJ =

+125°C

-10

60

nA

-IIB

3/

±VCC = ±15 V,

VCM = +10 V, t σ 25 ms

TJ = +25°C

-100

300

pA

TJ =

+125°C

-10

50

nA

±VCC = ±20 V,

-15 V σ VCM σ 0 V, t σ 25 ms

TJ = +25°C

-100

100

pA

TJ =

+125°C

-10

50

nA

Power supply rejection

ratio

+PSRR

+VCC = 10 V, -VCC = -20 V

1,2,3

All

85

dB

-PSRR

+VCC = 20 V, -VCC = -10 V

85

Input voltage common    4/

mode rejection

CMR

±VCC = ±20 V,

VIN = ±15 V

1,2,3

All

85

dB

Adjustment for input

offset voltage

VIO

ADJ(+)

±VCC = ±20 V

1,2,3

All

+8

mV

VIO

ADJ(-)

-8

Output short circuit          5/

current (for positive output)

IOS(+)

±VCC = ±15 V, t σ 25 ms, (short circuit to ground)

1,2,3

All

-50

mA