TABLE III. Group A inspection for device type 01 - Continued. Terminal conditions (pins not designated may be H � 2.0 V, L ≤ 0.8 V or open)
Subgroup |
Symbol |
MIL- STD- 883 method |
Cases E, F |
1 |
2 |
3 |
4 |
5 |
6 |
7 |
8 |
9 |
10 |
11 |
12 |
13 |
14 |
15 |
16 |
Measured terminal |
Test limits |
Unit |
|
Test no. |
Clear |
Shift right |
Input A |
Input B |
Input C |
Input D |
Shift left |
GND |
S0 |
S1 |
Clock |
QD |
QC |
QB |
QA |
VCC |
Min |
Max |
|||||
10 TC=125°C |
fMAX |
5/ |
138 |
6/ |
IN |
GND |
GND |
GND |
GND |
GND |
GND |
5.0 V |
GND |
IN |
OUT |
5.0 V |
QD |
28.0 |
MHz |
||||
tPHL1 |
3003 5/ " " |
139 140 141 142 |
IN " " " |
5.0 V " " " |
5.0 V " " " |
5.0 V " " " |
5.0 V " " " |
" " " " |
5.0 V " " " |
5.0 V " " " |
IN " " " |
OUT |
OUT |
OUT |
OUT |
" " " " |
Clear/QA Clear/QB Clear/QC Clear/QD |
4 " " " |
28 " " " |
ns " " " |
|||
tPLH2 |
" " " " |
143 144 145 146 |
6/ " " " |
IN |
IN |
IN |
IN |
" " " " |
7/ " " " |
7/ " " " |
" " " " |
OUT |
OUT |
OUT |
OUT |
" " " " |
Clock/QA Clock/QB Clock/QC Clock/QD |
" " " " |
19 " " " |
" " " " |
|||
tPHL2 |
" " " " |
147 148 149 150 |
7/ " " " |
IN |
IN |
IN |
IN |
" " " " |
" " " " |
" " " " |
" " " " |
OUT |
OUT |
OUT |
OUT |
" " " " |
Clock/QA Clock/QB Clock/QC Clock/QD |
" " " " |
25 " " " |
" " " " |
|||
11 |
Same tests, terminal conditions, and limits as subgroup 10, except TC = -55°C. |
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NOTES:
1/ Input is a single clock pulse.
2/ IIL = limits shall be as follows:
Measured terminal |
min/max limits (mA) for circuit |
|||
A |
B |
C |
D |
|
Clear, S0, S1 |
-0.7/-1.3 |
-1/-2 |
-1/-2 |
-1/-2 |
Shift R, Shift L, A, B, C, D, Clock |
-1/-2 |
-1/-2 |
-1/-2 |
-1/-2 |
3/ A = terminal connected to 2.0 V minimum. B = terminal connected to 0.8 V maximum.
4/ Tests shall be performed in the sequence specified. Output voltages shall be either high "H" or "L" as indicated in the terminal conditions columns.
Output voltage test limits over the specified temperature range shall be either: (1) H = 2.5 V minimum and L = 0.5 V maximum when using a high speed checker double comparator, or (2) H > 1.5 V and L < 1.5 V when using a high speed checker single comparator.
5/ See figure 4 herein for switching test circuit and waveforms.
6/ The clear input is momentarily grounded, then raised to and held at 3.0 V minimum/5.5 V maximum.
7/ 3.0 V minimum, 5.0 V maximum.
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