MIL-M-38510-76 Microcircuits, Digital, Bipolar Schottky Ttl, Cascadable, Shift Registers, Monolithic SiliconThis specification covers the detail requirements for monolithic, silicon, Schottky TTL, shift register microcircuits. Two product assurance classes and a choice of case outlines and lead finishes are provided for each type and are reflected in the complete part number. For this product, the requirements of MIL-M-38510 have been superseded by MIL-PRF-38535, see 6.4.

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MIL-M-3851O/76C

Device type O1

The register has four modes of operation:

Parallel (broadside) load

Shift right (in the direction QA toward QD) Shift left (in the direction QD toward QA) Inhibit clock (do nothing)

Synchronous parallel loading is accomplished by applying the four bits of data and taking both mode control inputs, SO and S1, high.  The data are loaded into the associated flip-flops and appear at the outputs after the positive transition of the clock input.  During loading, serial data flow is inhibited.

Shift right is accomplished synchronously with the rising edge of the clock pulse when SO is high and S1 is low. Serial data for this mode is entered at the shift right data input.  When SO is low and S1 is high, data shifts left synchronously and new data is entered at the shift left serial input.  Clocking of the flip-flop is inhibited when both mode control inputs are low.

H = high level (steady state) L = low level (steady state)

x = irrelevant (any input, including transitions)

t  = transition from low to high level

a, b, c, d, = the level of steady state input at inputs A, B, C, or D, respectively.

QAO, QBO, QCO, QDO = the level of QA, QB, QC, or QD, respectively, before the indicated steady state input conditions were established.

QAn, QBn, QCn, QDn = the level of QA, QB, QC, or QD, respectively, before the most recent   t  transition of the clock.

Figure 2.  Truth tables and timing diagrams.

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