MIL-M-38510-380 Microcircuits, Digital, Bipolar, Advanced Low Power Schottky Ttl, Binary Counters, Cascadable, Monolithic SiliconThis specification covers the detail requirements for monolithic silicon, advanced low power Schottky TTL, binary counters. Two product assurance classes and a choice of case outlines and lead finishes are provided for each type and are reflected in the complete part number. For this product, the requirements of MIL-M-38510 have been superseded by MIL-PRF-38535, see 6.3.

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MIL-M-38510/3808

1.3  Absolute maximum ratings.

Supply voltage range .............................................................................. -0.5 V dc to +7.0 V dc

Input voltage range ................................................................................. -1.5 V dc at -18 mA to +7.0 V dc

Storage temperature range  .................................................................... -65° to +150°C Maximum power dissipation, per device (PD)  1/

Device types 01 and 02 .................................................................... 115 mW

Device type 03 .................................................................................. 137.5 mW Device type 04 .................................................................................. 198 mW

Device type 05 .................................................................................. 176 mW

Lead temperature (soldering, 10 seconds) ............................................. +300°C

Thermal resistance, junction to case (eJC) .............................................. (See MIL-STD-1835) Junction temperature (TJ) 2/ ................................................................... 175°C

1.4  Recommended operating conditions.

Maximum low level output current (IOL):

Device types 01, 02, and 03  ............................................................. 4.0 mA

Device types 04 and 05 .................................................................... 12.0 mA

Supply voltage (VCC) ............................................................................... 4.5 V dc minimum to 5.5 V dc maximum

Minimum high level input voltage (VIH)  ................................................... 2.0 V dc Maximum low level input voltage (VIL)  .................................................... 0.8 V dc Normalized fanout (each output)  3/ :

At low logic level ............................................................................... 10 maximum

At high logic level  ............................................................................. 20 maximum

Input clock frequency (fMAX)

+25°C;

Device types 01 and 02  ............................................................... 40 MHz

Device types 03, 04, and 05  ........................................................ 30 MHz

-55°C/+125°C;

Device types 01 and 02  ............................................................... 35 MHz

Device types 03, 04, and 05  ........................................................ 25 MHz

Width of clock pulse (tP  CLOCK)

+25°C;

Device types 01 and 02  ............................................................... 12.5 ns

Device types 03  ........................................................................... 15 ns

-55°C/+125°C;

Device types 01 and 02  ............................................................... 14 ns

Device types 03  ........................................................................... 20 ns

+25°C;

Device types 04 and 05  ............................................................... 16.5 ns

-55°C/+125°C;

Device types 04 and 05  ............................................................... 20 ns

Width of asynchronous clear pulse (tP  ACLR):

Device types 01, 04, and 05  ............................................................. 20 ns

1/  Must withstand the added PD  due to short-circuit test (e.g., IOS).

2/  Maximum junction temperature should not be exceeded except in accordance with allowable short

duration burn-in screening condition in accordance with MIL-PRF-38535.

3/  The device should fanout in both high and low levels to specified number of inputs of the same device type as that being tested.

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