MIL-M-38510-372 Microcircuits, Digital, Bipolar, Advanced Low Power Schottky Ttl, Flip-Flops Cascadable, Monolithic SiliconThis specification covers the detail requirements for monolithic silicon, advanced low power Schottky TTL, flip-flops, bistable logic microcircuits. Two product assurance classes and a choice of case outlines and lead finishes are provided for each type and are reflected in the complete part number. For this product, the requirements of MIL-M-38510 have been superseded by MIL-PRF-38535, see 6.3.

Pages 1 - 2 - 3 - 4 - 5 - 6 - 7 - 8 - 9 - 10 - 11 - 12 - 13 - 14 - 15 - 16 - 17 - 18 - 19 - 20 - 21 - 22 - 23 - 24 - 25 - 26 - 27 - 28 - 29 - 30 - 31 - 32 - 33 - 34 - 35 - 36 - 37

MIL-M-38510/3728

NOTES:

1. Clock input pulse characteristics: t1 = t0 = 6 ±1.5 ns; tP(CLK) = 12.5 ns; PRR � 1.0 MHz.

2. Q output applies to device type 02 only.

3. D input pulse characteristics: t1 = t0 = 6 ±1 ns; t(SETUP) = 15 ns; t(HOLD) = 0 ns; tP = 15 ns; PRR is 50% of clock PRR.

4. For fMAX, the clock input pulse characteristics are as follows: t1 = t0 � 3 ns; for 25°C, tP(CLK) = 10 ns; PRR = 50

MHz; for -55/125°C, tP(CLK) = 12.5 ns, PRR = 40 MHz. The D input pulse shall be one-half of the frequency of the clock and the D i and ↓ shall be coincident with the clock ↓ , but may be offset sufficiently to assure

adequate tSETUP and tHOLD (see 1.4). t1 = t0 � 3ns.

5. Inputs not under test are at ground.

6. CL = 50 pF ±10%, including scope probe, wiring, and stray capacitance without package in test fixture.

7. RL = 499n ±1%.

8. Voltage measurements are to be made with respect to network ground terminal.

FIGURE 4. Synchronous switching test circuit (high-level data) types 01 and 02 - Continued.