MIL-M-38510-372 Microcircuits, Digital, Bipolar, Advanced Low Power Schottky Ttl, Flip-Flops Cascadable, Monolithic SiliconThis specification covers the detail requirements for monolithic silicon, advanced low power Schottky TTL, flip-flops, bistable logic microcircuits. Two product assurance classes and a choice of case outlines and lead finishes are provided for each type and are reflected in the complete part number. For this product, the requirements of MIL-M-38510 have been superseded by MIL-PRF-38535, see 6.3.

Pages 1 - 2 - 3 - 4 - 5 - 6 - 7 - 8 - 9 - 10 - 11 - 12 - 13 - 14 - 15 - 16 - 17 - 18 - 19 - 20 - 21 - 22 - 23 - 24 - 25 - 26 - 27 - 28 - 29 - 30 - 31 - 32 - 33 - 34 - 35 - 36 - 37

MIL-M-38510/3728

1.3  Absolute maximum ratings.

Supply voltage range  .............................................................................  -0.5 V dc to +7.0 V dc

Input voltage range  ................................................................................  -1.5 V dc at -18 mA to +7.0 V dc

Storage temperature range  ....................................................................  -65° to +150°C Maximum power dissipation (PD), per device:  1/

Device 01  .........................................................................................  104.5 mW

Device 02  .........................................................................................    77 mW Device 03  .........................................................................................  148.5 mW

Device 04  .........................................................................................  170.5 mW

Lead temperature (soldering, 10 seconds) .......................................  +300°C Thermal resistance, junction to case (eJC):

Cases E, F, R, S, and 2 ........................................................................  (See MIL-STD-1835)

Junction temperature (TJ) 2/ ...................................................................  175°C

1.4  Recommended operating conditions.

Supply voltage (VCC)  ..............................................................................  4.5 V dc minimum to 5.5 V dc maximum

Minimum high level input voltage (VIH) ...................................................  2.0 V dc

Maximum low level input voltage (VIL) ....................................................  0.8 V dc

Normalized fanout (each output) 3/ ........................................................  10 maximum at low logic level

20 maximum at high logic level

Case operating temperature range (TC)  .................................................  -55° to +125°C Minimum width of clock pulse (tP(CLK))

type 01, 02    25°C    .........................................................................  10 ns

-55/125°C    ..................................................................  12.5 ns type 04          25°C    .........................................................................  14 ns

-55/125°C    ..................................................................  16.5 ns

Minimum width of clear pulse (tP(CLEAR))

type 01, 02  .......................................................................................  15 ns

Minimum width of enable pulse (tP(ENA8LE))

type 03  .............................................................................................  10 ns

Minimum setup time before clock (tSETUP)

type 01, 02  .......................................................................................  16 ns

type 04  .............................................................................................  10 ns

Minimum hold time after clock (tHOLD)

type 01, 02  .......................................................................................  0 ns

type 04  .............................................................................................  4 ns

Minimum setup time before enable (tSETUP)

type 03  .............................................................................................  10 ns

Minimum hold time after enable (tHOLD)

type 03  .............................................................................................  7 ns

Minimum clear inactive state time before clock

type 01, 02  .......................................................................................  8 ns

1/  Must withstand the added PD  due to short-circuit test (e.g., IOS).

2/  Maximum junction temperature should not be exceeded except in accordance with allowable short

duration burn-in screening condition in accordance with MIL-PRF-38535.

3/  The device should fanout in both high and low levels to the specified number of inputs of the same device type as that being tested.

2