MIL-M-38510/316E
Device type 03 and 05
Inputs |
Output of addressed latch |
Each other output |
Function |
|
Clear |
Enable |
|||
H |
L |
D |
Qio |
Addressable latch |
H |
H |
Qio |
Qio |
Memory |
L |
L |
D |
L |
8-line demultiplexer |
L |
H |
L |
L |
Clear |
Latch Selection Table
Select inputs |
Latch addressed |
||
C |
B |
A |
|
L |
L |
L |
0 |
L |
L |
H |
1 |
L |
H |
L |
2 |
L |
H |
H |
3 |
H |
L |
L |
4 |
H |
L |
H |
5 |
H |
H |
L |
6 |
H |
H |
H |
7 |
H = high level, L = low level
Q = the level at the data input
Qio = the level of Qi (i = 0,1,….,7, as appropriate) before
the indicated steady-state input conditions were established.
FIGURE 2. Truth tables - Continued.
10
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