MIL-M-38510/178
Truth table for each flip-flop |
||||
CLEAR |
CLOCK |
D |
Q |
Q * |
L |
x** |
x |
L |
H |
H |
↑ |
H |
H |
L |
H |
↑ |
L |
L |
H |
H |
L |
x |
Q0 |
Q0 |
* Device type 02 only.
** Input may be high, low or open circuit.
NOTE:
Clear is independent of clock. Information at the D input meeting the setup time requirements is transferred to the Q output on the positive going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive going pulse. When the clock input is either high or low level, the D input signal has no effect at the output.
FIGURE 3. Truth table.
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