MIL-M-38510-17 Microcircuits, Digital, Ttl, Flip-Flops, Monolithic SiliconThis specification covers the detail requirements for monolithic, silicon, TTL, bistable logic gating microcircuits. Two product assurance classes and a choice of case outlines and lead finishes are provided for each type and are reflected in the complete part number. For this product, the requirements of MIL-M-38510 have been superseded by MIL-PRF-38535, see 6.4.

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Test

Symbol

Conditions 1/

-55qC ≤ TC  ≤ +125qC

unless otherwise specified

Device type

Limits

Unit

Min

Max

High-level output voltage

VOH

VCC  = 4.5 V; IOH  = -800 µA

All

2.4

V

Low-level output voltage

VOL

VCC  = 4.5 V; IIN  = 16 mA

All

0.4

V

Input clamp voltage

VIC

VCC  = 4.5 V; IIN  = -12 mA; TC = 25qC

All

-1.5

V

Low-level input current

IIL1

VCC  = 5.5 V; VIN  = 0.4 V  2/

All

-0.3

-1.6

mA

IIL2

VCC  = 5.5 V; VIN  = 0.4 V  3/

All

-0.4

-1.6

mA

IIL3

VCC  = 5.5 V; VIN  = 0.4 V  4/

All

-0.3

-0.8

mA

High-level input current

IIH1

VCC  = 5.5 V; VIN  = 2.4 V

All

40

µA

IIH2

VCC  = 5.5 V; VIN  = 5.5 V

All

100

µA

Short-circuit output current

IOS

VCC  = 5.5 V; VIN  = 0

All

-20

-57

mA

Supply current per device

ICC

VCC  = 5.5 V; VIN  = 5.5 V

01

65

mA

02

45

mA

Maximum clock frequency

fMAX

VCC  = 5 V;

CL  = 50 pF ± 10% RL  = 390 n ± 5%

All

25

MHz

Propagation delay to high

logic level (clear to  Q)

tPLH1

02

5

36

ns

Propagation delay to low logic level (clear to Q)

tPHL1

All

5

50

ns

Propagation delay to high logic level (clock to Q)

tPLH2

All

5

43

ns

Propagation delay to low logic level (clock to Q)

tPHL2

All

5

43

ns

Propagation delay to high

logic level (clock to  Q)

tPLH3

02

5

43

ns

Propagation delay to low

logic level (clock to  Q)

tPHL3

02

5

43

ns