MIL-M-38510-11 Microcircuits, Digital, Ttl, Arithmetic Logic Units/Function Generators, Monolithic SiliconThis specification covers the detail requirements for monolithic, silicon, TTL, arithmetic logic units/ function generators. Two product assurance classes and a choice of case outlines and lead finishes are provided for each type and are reflected in the complete part number. For this product, the requirements of MIL-M-38510 have been superseded by MIL-PRF-38535, see 6.4.

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Test

Symbol

Conditions 1/

Device type

Limits

Unit

Min

Max

Cn to any  F   SUM  mode

tPHL7

VCC  =5.0 V  See figure 4

SUM  mode test table

01

7

25

ns

A I  or  BI  to A = B  DIFF  mode

tPHL8

VCC  = 5.0 V  See figure 4

DIFF  mode test table

01

7

76

ns

Cn or Cn+4  SUM  mode

tPHL9

VCC  = 5.0 V  See figure 4

SUM  mode test table

01

7

30

ns

Cn to Cn+4  DIFF  mode

tPHL10

VCC  = 5.0 V  See figure 4

DIFF  mode test table

01

7

30

ns

A I  or  BI  to Cn+4  SUM  mode

tPHL11

VCC  = 5.0 V  See figure 4

SUM  mode test table

01

7

41

ns

A I  or  BI  to Cn+4  DIFF  mode

tPHL12

VCC  = 5.0 V  See figure 4

DIFF  mode test table

01

7

50

ns

A I  or  BI  to any  F   logic mode

tPHL13

VCC  = 5.0 V  See figure 4 logic mode test table

01

7

49

ns

Propagation delay times, low-to-high level output:  5/

A I  or  BI  to any  F   SUM

mode

tPLH1

VCC  = 5.0 V  See figure 4

SUM  mode test table

01

7

60

ns

A I  or  BI  to any  F   DIFF

mode

tPLH2

VCC  = 5.0 V  See figure 4

DIFF  mode test table

01

7

69

ns

A I  or  BI  to  P    SUM  mode

tPLH3

VCC  = 5.0 V  See figure 4

SUM  mode test table

01

7

27

ns

A I  or  BI  to  P   DIFF  mode

tPLH4

VCC  = 5.0 V  See figure 4

DIFF  mode test table

01

7

40

ns

A I  or  BI  to  G   SUM  mode

tPLH5

VCC  = 5.0 V  See figure 4

SUM  mode test table

01

7

27

ns

A I  or  BI  to  G   DIFF  mode

tPLH6

VCC  = 5.0 V  See figure 4

DIFF  mode test table

01

7

40

ns

Cn to any  F   SUM  mode

tPLH7

VCC  = 5.0 V  See figure 4

SUM  mode test table

01

7

27

ns

A I  or  BI  to A = B  DIFF  mode

tPLH8

VCC  = 5.0 V  See figure 4

DIFF  mode test table

01

7

80

ns

Cn to Cn+4  SUM  mode

tPLH9

VCC  = 5.0 V  See figure 4

SUM  mode test table

01

7

28

ns

Cn to Cn+4  DIFF  mode

tPLH10

VCC  = 5.0 V  See figure 4

DIFF  mode test table

01

7

28

ns

A I  or  BI  to Cn+4  SUM  mode

tPLH11

VCC  = 5.0 V  See figure 4

SUM  mode test table

01

7

50

ns