MIL-M-38510-109 Microcircuits, Linear, Precision Timers, Monolithic SiliconThis specification covers the detail requirements for monolithic silicon, precision timers. Two product assurance classes and a choice of case outlines and lead finishes are provided and are reflected in the complete part number. For this product, the requirements of MIL-M-38510 have been superseded by MIL-PRF-38535, see 6.3

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Symbol

Description

VTR

Trigger voltage.  The voltage at which the output latches from the "low" state to the

"high" state.  This voltage is nominally 1/3 VCC.

ITR

Trigger current.  The current flowing out of the trigger terminal while the output is in the

"high" state.

VTH

Threshold voltage.  The voltage at which the output latches from the "high" state to the

"low" state.  This voltage is nominally 2/3 VCC.

ITH

Threshold current.  The current flowing into the threshold terminal while the output is in the "low" state.

VCL

Control voltage.  The control voltage is the reference voltage for the threshold

comparator.  It is internally generated by a voltage divider (from VCC to ground) tapped

at 2/3 VCC.  NOTE:  The divider is also tapped at 1/3 VCC, which is the reference voltage for the trigger comparator.

VR

Reset voltage.  The reset acts as an inhibit.  If 1.3 ≤ VR ≤ VCC, the device is free to function.  If 0 V ≤ VR ≤ 0.1 V, the output is forced to the "low" state.  The output will remain low after the reset voltage goes high only if the trigger voltage is high.  If the

trigger voltage is low, the output will go high when the reset voltage goes high.  The

reset voltage going low also causes the discharge transistor to turn on, thus preventing

the timing capacitor (CT) from charging.

IR

Reset current.  The current out of the reset terminal after the reset voltage has been

applied and the output is latched low.

VSAT

Discharge transistor saturation voltage.  When the output is low, the discharge terminal

is sinking current.  VSAT is defined as the collector-emitter voltage of the discharge transistor when sinking the specified current.

tD(OH)

Time delay, output high.  In the monostable mode of operation, the interval of time the output remains high once triggered.  This delay is given by the following equation:

tD(OH) = 1.1 RT CT (see figure 5).

tch

Capacitor charge time.  In the astable mode of operation, the time interval during which

the external timing capacitor (CT) is charging from 1/3 VCC to 2/3 VCC.  This interval is ideally given by the equation:  tch = 0.693 (RTA + RTB) CT (see figure 6).

tdis

Capacitor discharge time.  In the astable mode of operation, the time interval during

which the external timing capacitor (CT) is discharging from 2/3 VCC to 1/3 VCC.  This interval is ideally given by the equation:  tdis = 0.693 RTB CT (see figure 6).