TABLE III. Group A inspection for device types 01 and 02 - Continued.
Subgroup |
Symbol |
Test no. |
Adapter pin numbers 1/ |
Energ. relays |
Measured pin(s) |
Notes and equations |
Limits |
Unit |
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1 |
2 |
3 |
4 |
5 |
6 |
7 |
8 |
9 |
10 |
11 |
13 |
14 |
15 |
16 |
VN |
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C.L. adj. |
VREF |
Cur Sense |
Error Amp |
Comp |
CT |
RT |
Sync |
Output A |
VC |
Output B |
VIN |
Shut- down |
No. |
Val. |
Unit |
Min |
Max |
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- |
+ |
+ |
- |
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9 TC = +25°C |
tfA |
165 |
Open |
Pin 5 |
GND |
GND |
VREF |
GND |
Open |
4.7 nF to GND |
10 kn to GND |
Open |
1 nF to GND |
15 V |
1 nF to GND |
15 V |
GND |
K11, K12 |
11 |
t7 |
ns |
tfA = t7 12/ |
130 |
ns |
||
tfB |
166 |
" |
" |
" |
" |
" |
" |
" |
" |
" |
" |
" |
" |
" |
" |
" |
" |
14 |
t8 |
ns |
tfB = t8 12/ |
130 |
ns |
|||
10 TC = +125°C |
trA |
167 |
" |
" |
" |
" |
" |
" |
" |
" |
" |
" |
" |
" |
" |
" |
" |
" |
11 |
t9 |
ns |
trA = t9 12/ |
130 |
ns |
||
trB |
168 |
" |
" |
" |
" |
" |
" |
" |
" |
" |
" |
" |
" |
" |
" |
" |
" |
14 |
t10 |
ns |
trB = t10 12/ |
130 |
ns |
|||
tfA |
169 |
" |
" |
" |
" |
" |
" |
" |
" |
" |
" |
" |
" |
" |
" |
" |
" |
11 |
t11 |
ns |
tfA = t11 12/ |
130 |
ns |
|||
tfB |
170 |
" |
" |
" |
" |
" |
" |
" |
" |
" |
" |
" |
" |
" |
" |
" |
" |
14 |
t12 |
ns |
tfB = t12 12/ |
130 |
ns |
|||
11 TC = -55°C |
171 through 174 |
All test parameters, test conditions, equations, notes, and test limits are identical with those specified in table III, subgroup 10, TC = +125°C. |
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1/ Pin 12 = ground.
2/ To verify that the PWM latch is resetting properly, the output stage must resume switching after the completion of a PWM LATCH SET command.
To minimize the effects of self heating, the test must be completed within the first 50 ms of applied power. The minimum limit shall be equal to 0.49 times the oscillator frequency.
3/ t < 100 ms, continuous IOS will be less than indicated limits.
4/ Test may need to be preceeded by a PWM LATCH RESET pulse. To reset latch, see figure 6.
5/ Digital logic methods may be used to determine the "on" or "off" status of the outputs (pins 11, 14). The voltage applied to the VC pin (13) and the (min, max)
limits may then be changed to accommodate the appropriate logic levels.
6/ Measuring at trip point of latch.
7/ Voltage on pin 4 measured and or applied with respect to voltage at pin 3.
8/ Raise voltage on designated pin until both outputs are in the off state. (0.4 V maximum for type 01, 13 V minimum for type 02). See note 5.
9/ Lower voltage on designated pin until both outputs are in the off state. (0.4 V maximum for type 01, 13 V minimum for type 02). See note 5.
10/ To enable testing of the intended shutdown path, pin 1 must be pulled up by a minimum of 250 µA (at pin 1 = 0.5 V).
11/ For type 01 VOL and type 02 VOH, pin 8 = 5 V. For type 02 VOL and type 01 VOH, see note 13.
12/ Measured from 1 V to 11 V at device pins 11 and 14, to 12 (not at adapter pins), see table I, note 8.
13/ Toggle flip flop to turn on desired output (see figure 6).
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