MIL-M-38510/656A
TABLE I. Electrical performance characteristics - Continued.
Test |
Symbol |
Conditions 1/ -55°C ≤ TC ≤ +125°C unless otherwise specified |
Device type |
VCC |
Limits |
Unit |
|
Min |
Max |
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Propagation delay time, clock to outputs |
tPHL2, tPLH2 5/, 6/ |
CL = 50 pF ± 10% |
01 |
4.5V |
37 |
ns |
|
02, 52 |
42 |
ns |
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03 |
37 |
ns |
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04 |
42 |
ns |
|||||
05 |
42 |
ns |
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06 |
41 |
ns |
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Output enable time |
tPZH, tPZL 5/, 6/ |
CL = 50 pF ± 10% RL = 1 kO ± 10% |
02 |
4.5V |
35 |
ns |
|
52 |
41 |
ns |
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04 |
35 |
ns |
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05 |
41 |
ns |
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06 |
35 |
ns |
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Output disable time |
tPHZ, tPLZ 5/, 6/ |
CL = 50 pF ± 10% RL = 1 kO ± 10% |
02 |
4.5V |
35 |
ns |
|
52 |
41 |
ns |
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04 |
35 |
ns |
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05 |
35 |
ns |
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06 |
35 |
ns |
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Transition time |
tTHL, tTLH 5/, 6/ |
CL = 50 pF ± 10% |
01 |
4.5V |
20 |
ns |
|
02, 52 |
16 |
ns |
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03 |
20 |
ns |
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04 |
16 |
ns |
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05 |
16 |
ns |
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06 |
16 |
ns |
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Maximum frequency test |
fMAX 5/, 6/ |
CL = 50 pF ± 10%, 50% duty cycle |
01 |
4.5V |
23 |
MHz |
|
02 |
25 |
MHz |
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52 |
21 |
MHz |
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03 |
21 |
MHz |
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04 |
25 |
MHz |
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05 |
25 |
MHz |
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06 |
25 |
MHz |
1/ Complete terminal conditions shall be as specified in table III.
2/ Guaranteed but not tested.
3/ IOZL set internal D flip-flops to high state.
IOZH set internal D flips-flops to low state.
4/ Power dissipation capacitance (CPD) per gate typically equals 25 pF.
5/ Tested at VCC = 4.5 V at +125°C for sample testing and VCC = 4.5 V at +25°C for screening.
Guaranteed at other VCC voltages and temperatures, see table IA and IB as appropriate and the
exception in 4.4.1d.
6/ See the formula for determining switching times and maximum frequencies shown in tables IA and
IB respectively.
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