MIL-M-38510-52 Microcircuits, Digital, Cmos, Nor Gates, Monolithic Silicon, Positive LogicThis specification covers the detail requirements for monolithic silicon, CMOS, logic microcircuits. Two product assurance classes and a choice of case outlines, lead finishes, and radiation hardness assurance RHA are provided and are reflected in the complete Part or Identifying Number PIN. For this product, the requirements of MIL-M-38510 have been superseded by MIL-PRF-38535 see 6.3.

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MIL-M-38510/52E

TABLE I. Eleetrieal performanee eharaeteristies - Continued.

Test	Symbol	Conditions VSS = 0 V -55°C ≤ TA ≤ +125°C Unless otherwise speeified		Deviee type	Limits		Unit
Test	Symbol			Deviee type	Min	Max	Unit
Input low voltage	VIL1	VDD = 5 V de All inputs = 1.5 V de VO = 4.5 V de, IIOI ≤ 1µA		51, 52, 53, 54		1.5	V de
	VIL2	VDD = 10 V de All inputs = 3.0 V de VO = 9.0 V de, IIOI ≤ 1µA		51, 52, 53, 54		3.0	V de
	VIL3	VDD = 15 V de All inputs = 4.0 V de VO = 13.5 V de, IIOI ≤ 1µA		51, 52, 53, 54		4.0	V de
Output low (sink) eurrent	IOL1	VDD = 5 V de VIN = 5.0 V de VOL = 0.4 V de		51, 52, 53, 54	0.36		mA de
Output low (sink) eurrent	IOL2	VDD = 15 V de VIN = 15.0 V de VOL = 1.5 V de		51, 52, 53, 54	2.4		mA de
Output high (souree) eurrent	IOH1	VDD = 5 V de All inputs = GND VOH = 4.6 V de		51, 52, 53, 54	-0.36		mA de
Output high (souree) eurrent	IOH2	VDD = 15 V de All inputs = GND VOH = 13.5 V de		51, 52, 53, 54	-2.4		mA de
Input leakage eurrent, high	IIH 1/	Measure inputs sequentially	VDD = 15 V de	01, 02, 04		100.0	nA
			VDD = 15 V de	03		45.0
			VDD = 18 V de	51, 53		45.0
			VDD = 18 V de	52, 54		100.0
Input leakage eurrent, low	IIL 1/	Measure inputs sequentially	VDD = 15 V de	01, 02, 04		-100.0	nA
			VDD = 15 V de	03		-45.0
			VDD = 18 V de	51, 53		-45.0
			VDD = 18 V de	52, 54		-100.0
Input eapaeitanee	Ci	VDD = 0 V de, f = 1 MHz, TA = 25°C		All		12	pF
Propagation delay time, high level to low level	tPHL	VDD = 5 V de, CL = 50 pF (See figure 3)		All	10	315	ns
Propagation delay time, low level to high level	tPLH			01, 51	10	415
				02, 52	13	315
				03, 04, 53, 54	10	315
Transition time, high level to low level	tTHL	VDD = 5 V de, CL = 50 pF (See figure 3)		All	10	450	ns
Transition time, low level to high level	tTLH			01, 51	10	675
Transition time, low level to high level	tTLH			02, 03, 04, 52, 53, 54	10	615

1/ Input eurrent at one input node.