MIL-M-38510/3438
1.3 Absolute maximum ratings.
Supply voltage range ............................................................................. -0.5 V dc to +7.0 V dc
Input voltage range ................................................................................ -1.2 V dc at -18 mA to +7.0 V dc
Storage temperature range .................................................................... -65° to +150°C Maximum power dissipation, per device (PD) 1/
Device types 01, 02, 03, 04 .............................................................. 303 mW
Lead temperature (soldering, 10 seconds) ............................................. +300°C
Thermal resistance, junction to case (eJC): ............................................. (See MIL-STD-1835) Junction temperature (TJ) 2/ ................................................................... 175°C
1.4 Recommended operating conditions.
Supply voltage (VCC) .............................................................................. 4.5 V dc minimum to
5.5 V dc maximum
Minimum high level input voltage (VIH) ................................................... 2.0 V dc Maximum low level input voltage (VIL) .................................................... 0.8 V dc Normalized fanout (each output) 3/
Low logic level .................................................................................. 33 maximum
High logic level ................................................................................. 50 maximum
Case operating temperature range (TC) ................................................. -55° to +125°C Width of clock pulse, high (PE = High)
Device types 01, 02 .......................................................................... 9.0 ns minimum
Width of clock pulse, high (PE = Low)
Device types 01, 02 .......................................................................... 7.0 ns minimum
Width of clock pulse, low ( PE = High)
Device types 01, 02 .......................................................................... 8.0 ns minimum
Width of clock pulse, low ( PE = Low)
Device types 01, 02 .......................................................................... 9.0 ns minimum
Width of master reset pulse, low ( MR = low)
Device type 01 ................................................................................. 9.5 ns minimum
Width of PL pulse low:
Device type 03 ................................................................................. 8.5 ns minimum
Device type 04 ................................................................................. 7.5 ns minimum
Width of clock pulse low:
Device type 03 ................................................................................. 7.0 ns minimum
Width of CPU or CPD pulse low
Device type 04 ................................................................................. 7.0 ns minimum
Width of master reset pulse, high (MR = high)
Device type 04 ................................................................................. 6.0 ns minimum
Width of CPU or CPD pulse, low (change of direction)
Device type 04 ................................................................................. 12.0 ns minimum
Setup time Pn high to clock pulse
Device types 01, 02 .......................................................................... 5.5 ns minimum
Setup time Pn low to clock pulse
Device types 01, 02 .......................................................................... 5.5 ns minimum
Setup time PE or SR high to clock pulse
Device types 01, 02 .......................................................................... 13.5 ns minimum
Setup time PE or SR low to clock pulse
Device types 01, 02 .......................................................................... 10.5 ns minimum
1/ Must withstand the added PD due to short-circuit test (e.g., IOS).
2/ Maximum junction temperature shall not be exceeded except in accordance with allowable short
duration burn-in screening condition in accordance with MIL-PRF-38535.
3/ The device shall fanout in both high and low levels to the specified number of inputs of the same device type as that being tested.
2
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