MIL-M-38510/158
TA8LE I. Electrical performance characteristics.
Test |
Symbol |
Conditions -55qC ≤ TC ≤ +125qC unless otherwise specified |
Device types |
Limits |
Unit |
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Min |
Max |
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High level output voltage |
VOH |
VCC = 4.5V; VIN = 0.8V |
IOH = -400µA |
01, 02 |
2.4 |
V |
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IOH = -800µA |
03, 04 |
2.4 |
V |
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Low level output voltage |
VOL |
VCC = 4.5V; VIN = 2.0V |
IOL = 16 mA |
01,02,04 |
0.4 |
V |
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IOL = 14.4 mA |
03 |
0.4 |
V |
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Input clamp voltage |
VIC |
VCC = 4.5 V; VIN = -12 mA |
All |
-1.5 |
V |
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Low level input current, data |
IIL1 |
VCC = 5.5 V; VIN = 0.4 V |
01, 02 |
-1.4 |
-3.2 |
mA |
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03 4/ |
-0.5 |
-2.4 |
mA |
|||||
04 |
-0.7 |
-2.7 |
mA |
|||||
Low level input curre |
nt Clock |
IIL2 |
VCC = 5.5 V; VIN = 0.4 V 1/ |
01, 02 |
-2.8 |
-6.4 |
mA |
|
Master reset and enable |
03, 04 |
-0.7 |
-1.6 |
mA |
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Set |
04 |
-0.7 |
-1.6 |
mA |
||||
High level input current, data |
IIH1 |
VCC = 5.5 V; VIN = 2.4 V 1/ |
01, 02 |
80 |
µA |
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03 |
40 |
µA |
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04 |
60 |
µA |
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High level input current, data |
IIH2 |
VCC = 5.5 V; VIN = 5.5 V 1/ |
01, 02 |
200 |
µA |
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03, 04 |
100 |
µA |
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High level input curre |
nt Clock |
IIH3 |
VCC = 5.5 V; VIN = 2.4 V 1/ |
01, 02 |
160 |
µA |
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Master reset and enable |
03, 04 |
40 |
µA |
|||||
Set |
04 |
40 |
µA |
|||||
High level input curre |
nt Clock |
IIH4 |
VCC = 5.5 V; VIN = 5.5 V 1/ |
01, 02 |
400 |
µA |
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Master reset and enable |
03, 04 |
100 |
µA |
|||||
Set |
04 |
100 |
µA |
|||||
Short circuit output current |
IOS |
VCC = 5.5 V 2/ 3/ |
01, 02 |
-20 |
-57 |
mA |
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03 5/ |
-10 |
-70 |
mA |
|||||
04 |
-20 |
-100 |
mA |
|||||
Supply current |
ICC |
VCC = 5.5 V 2/; VIN = 4.5 V |
01, 02 |
46 |
mA |
|||
03 |
106 |
mA |
||||||
04 |
55 |
mA |
||||||
Propagation delay time for types 01 and 02 |
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To high level, from D input to Q output |
tPLH1 |
CL = 50 pF ± 10%; RL = 390 ohms ± 5% |
01, 02 |
2 |
44 |
ns |
||
To high level, from D input to Q output |
tPLH2 |
01 |
2 |
55 |
ns |
|||
To low level, from D input to Q output |
tPHL1 |
01, 02 |
2 |
38 |
ns |
|||
To low level, from D input to Q output |
tPHL2 |
01 |
2 |
25 |
ns |
|||
To low level, from clock input to Q output |
tPHL3 |
01 |
2 |
25 |
ns |
See footnotes at end of table.
4
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