MIL-M-38510-320 Microcircuits, Digital, Bipolar Low-Power Schottky Ttl. Counters, Cascadable, Monolithic SiliconThis specification covers the detail requirements for monolithic silicon, low-power Schottky TTL, binary and decade counters. Two product assurance classes and a choice of case outlines and lead finishes are provided for each type and are reflected in the complete part number. For this product, the requirements of MIL-M- 38510 have been superseded by MIL-PRF-38535, see 6.3.

Pages 1 - 2 - 3 - 4 - 5 - 6 - 7 - 8 - 9 - 10 - 11 - 12 - 13 - 14 - 15 - 16 - 17 - 18 - 19 - 20 - 21 - 22 - 23 - 24 - 25 - 26 - 27 - 28 - 29 - 30 - 31 - 32 - 33 - 34 - 35 - 36 - 37

MlL-M-38510/320D

1/ Cases X and 2 pins not referenced are NC.

2/ lnput CP1 shall be connected to Q0 during the VOL test.

3/ llL limits are as follows:

Test	Min/Max limits for circuits
Test	B	C	E	F
llL1	-320/-800 µA	-180/-410 µA	-280/-760 µA	-120/-360 µA
llL4	-160/-400 µA	-150/-380 µA	-160/-400 µA	-120/-360 µA
llL5	-1.0/-2.4 mA	-1.2/-2.6 mA	-0.6/-1.6 mA	-1.0/-2.4 mA
llL6	-0.4/-1.4 mA	-1.2/-2.6 mA (Device 01)	-0.8/-2.8 mA (Device 01)	-1.3/-3.2 mA (Device 01)
llL6	-0.4/-1.4 mA	-.62/-1.35 mA (Device 02)	-0.4/-1.4 mA (Device 02)	-.65/-1.6 mA (Device 02)

4/ A = 2.5 V, B = 0.4 V.

5/ Only a summary of attributes data is required.

6/ Output voltages shall be either:

a. H � 1.5 V

b. L � 1.5 V

7/ lf proper setup is achieved from previous test and conditions, no additional setup is required. (See figure 4). When testing

tPHL3 or tPLH3, the Q0 pin shall be connected to the CP1 pin

8/ The fMAX minimum limit is the frequency of the input pulse. Outputs shall be monitored and shall be observed to toggle per the truth table for that device type. Recommended operating conditions (particularly for tp(lN)) shall be observed.

9/ Setup to count 3 (Q0 = 1, Q1 = 1, Q2 = 0, Q3 = 0) by either:

a. Serial up count (3 clock pulses; PL high).

b. Parallel load to count 3 (D0 = 1, D1 = 1, D2 = 0, D3 = 0; following data setup as shown, make PL low, then high. Following the above setup, apply clock pulse to CPo ( PL high) for test. (See figure 4, connect Q0 to CP1 .)

10/ Setup to count 7 (Q0 = 1, Q1 = 1, Q2 = 1, Q3 = 0) by either:

a. Serial up count (7 clock pulses; PL high).

b. Parallel load to count 7 (D0 = 1, D1 = 1, D2 = 1, D3 = 0; following data setup as shown, make PL low, then high. Following the above setup, apply clock pulse to CPo ( PL high) for test. (See figure 4, connect Q0 to CP1 .)

11/ Setup to count 6 (Q0 = 0, Q1 = 1, Q2 = 1, Q3 = 0) by either:

a. Serial up count (3 clock pulses at CP1 , PL high).

b. Parallel load to count 6 (D0 = 0, D1 = 1, D2 = 1, D3 = 0; following data setup as shown, make PL low, then high. Following the above setup, apply clock pulse to CP1 ( PL high) for test. (See figure 4)

12/ Setup to count 8 (for device type 01) (Q0 = 0, Q1 = 0, Q2 = 0, Q3 = 0) or count 14 (for device type 02) (Q0 = 1, Q1 = 1, Q2

= 0, Q3 = 1) by either;

a. Serial up count (4 clock pulses at CP1 for device type 01; 7 clock pulses at CP1 for device type 02; PL high).

b. Parallel load to count 8 (D0 = 0, D1 = 0, D2 = 0, D3 = 1) for device type 01 or count 14 (D0 = 0, D1 = 1, D2 = 1, D3 = 1)

for device type 02; following data setup as shown, make PL low, then high.

Following the above setup, apply clock pulse to CP1 ( PL high) for test. (See figure 4)

13/ The maximum limit for device type 01 is 29 ns, 02 is 60 ns.

14/ The maximum limit for device type 01 is 40 ns, 02 is 85 ns.

15/ The output under test must be set to logical 0 previous to test. This may be done by setting MR low, then high, or as follows: Dn = low followed by pulse on PL . Set Dn = high, pulse on PL to run test. (See figure 4).

16/ The output under test must be set to logical 1 previous to test. This may be done by setting Dn = high followed by pulse on

PL . Set Dn = low, pulse on PL to run test. (See figure 4).

17/ The maximum limit for device type 01 is 38 ns, 02 is 78 ns.

18/ The maximum limit for device type 01 is 52 ns, 02 is 110 ns.