MIL-M-38510-1 Microcircuits, Digital, Ttl, Nand Gates, Monolithic SiliconThis specification covers the detail requirements for monolithic silicon, TTL, positive NAND logic gating microcircuits. Two product assurance classes and a choice of case outlines and lead finishes are provided for each type and are reflected in the complete part number. For this product, the requirements of MIL-M-38510 have been superseded by MIL-PRF-38535, see 6.3.

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Test

Symbol

Conditions

-55°C ≤ TC  ≤ +125°C

Device

types

Limits

Unit

Min

Max

High level output voltage

VOH

VCC  = 4.5 V,  VIN  = 0.8 V, IOH  = -400 µA   1/

01, 02,

03, 04,

05

2.4

- - -

V

Low level output voltage

VOL

VCC  = 4.5 V,  IOL  = 16 mA,

VIN  = 2.0 V for all inputs of gate under test        1/

All

0.4

V

Input clamp voltage

VI C

VCC  = 4.5 V, IIN  = -12 mA

TC = 25°C

All

-1.5

V

Maximum collector cut-off current

ICEX

VCC  = 4.5 V,  VIN  = 0.8 V, VOH  = 5.5 V

06, 07

08, 09

250

µA

High level input

current

IIH1

VCC  = 5.5 V, VIN  = 2.4 V     2/

All

40

µA

High level input

current

IIH2

VCC  = 5.5 V, VIN  = 5.5 V     2/

All

100

µA

Low level input

current

IIL

VCC  = 5.5 V, VIN  = 0.4 V     1/

All

-0.7

-1.6

mA

Short circuit output current

I OS

VCC  = 5.5 V     2/  3/

01, 02,

03, 04,

05

-20

-55

mA

High level supply

current per gate

I CCH

VCC  = 5.5 V, VIN  = 0 V     2/

All

1.65

mA

Low level supply

current per gate

I CCL

VCC  = 5.5 V, VIN  = 5.5 V     1/

All

5.0

mA

Propagation delay time, high-to-low level

tPHL

CL  = 50 pF, RL  = 390n

01, 02,

03, 04,

05

3

24

ns

06, 07,

08, 09

3

29

ns

Propagation delay time, low-to-high level

tPLH

CL  = 50 pF, RL  = 390n

01, 02,

03, 04,

05

3

27

ns

06, 07,

08, 09

3

35

ns