MIL-M-38510-78 Microcircuits, Digital, Schottky Ttl, Arithmetic Logic Unit / Function Generators, Monolithic SiliconThis specification covers the detail requirements for monolithic silicon, Schottky TTL, arithmetic logic unit / function generators. Two product assurance classes and a choice of case outlines and lead finishes are provided and are reflected in the complete part number. For this product, the requirements of MIL-M-38510 have been superseded by MIL-PRF-38535, see 6.4.

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Test

Symbol

Conditions   1/

-55°C ≤ TC ≤ +125°C Unless Otherwise Specified

Device type

Limits

Unit

Min

Max

Propagation delay times, high-to-low level output:  9/

Ai or Bi to P

diff mode

tPHL4

VCC = 5.0 V  See figure 4 diff mode test table

01

2

20

ns

Ai or Bi to G

sum mode

tPHL5

VCC = 5.0 V  See figure 4 sum mode test table

01

2

16

ns

Ai or Bi to G

diff mode

tPHL6

VCC = 5.0 V  See figure 4 diff mode test table

01

2

20

ns

Cn to any F0 sum mode

tPHL7

VCC = 5.0 V  See figure 4 sum mode test table

01

2

16

ns

Ai or Bi to A = B

diff mode

tPHL8

VCC = 5.0 V  See figure 4 diff mode test table

01

2

42

ns

Cn to Cn+4

sum mode

tPHL9

VCC = 5.0 V  See figure 4 sum mode test table

01

2

14.5

ns

Cn to Cn+4

diff mode

tPHL10

VCC = 5.0 V  See figure 4 diff mode test table

01

2

14.5

ns

Ai or Bi to Cn+4

sum mode

tPHL11

VCC = 5.0 V  See figure 4 sum mode test table

01

2

25

ns

Ai or Bi to Cn+4

diff mode

tPHL12

VCC = 5.0 V  See figure 4 diff mode test table

01

2

29

ns

Ai or Bi to any F

logic mode

tPHL13

VCC = 5.0 V  See figure 4 logic mode test table

01

2

28

ns

Propagation delay times, low to high level output:   9/

Ai or Bi to any F

sum mode

tPLH1

VCC = 5.0 V  See figure 4 sum mode test table

01

2

23

ns

Ai or Bi to any F

diff mode

tPLH2

VCC = 5.0 V  See figure 4 diff mode test table

01

2

26

ns

Ai or Bi to P

sum mode

tPLH3

VCC = 5.0 V  See figure 4 sum mode test table

01

2

16

ns