MIL-M-38510-74 Microcircuits, Digital, Bipolar, Schottky Ttl, And-Or-Invert Gates, Monolithic SiliconThis specification covers the detail requirements for monolithic silicon, Schottky TTL, AND-OR-INVERT logic gating microcircuits. Two product assurance classes and a choice of case outlines and lead finishes are provided and are reflected in the complete part number. For this product, the requirements of MIL-M-38510 have been superseded by MIL-PRF-38535, see 6.4.

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Test

Symbol

Conditions

-55°C ≤ TC  ≤ +125°C

Device type

Limits

Unit

Min

Max

High level output voltage

VOH

VCC  = 4.5 V, VIN  = 0.8 V IOH  = -1 mA  1/

TC  = +125°C, VIN  = 0.7 V

01, 02

2.5

---

V

Low level output voltage

VOL

VCC  = 4.5 V, IOL  = 20 mA VIN  = 2.0 V for all inputs of gate under test  2/

01, 02,

03

---

0.5

V

TC  = +125°C

0.45

V

Input clamp voltage

VIC

VCC  = 4.5 V, IIN  = -18 mA TC = 25°C

01, 02,

03

---

-1.2

V

High level input current

IIH1

VCC  = 5.5 V, VIN  = 2.7 V  2/

01, 02,

03

---

50

µA

High level input current

IIH2

VCC  = 5.5 V, VIN  = 5.5 V  2/

01, 02,

03

---

1.0

mA

Low level input current

IIL

VCC  = 5.5 V, VIN = 0.5 V  1/

01, 02,

03

-1.0

-2.0

mA

Short circuit output current

IOS

VCC  = 5.5 V  3/

01, 02

-40

-100

mA

High level supply current

ICCH

VCC  = 5.5 V VIN  = 0 V

01

---

18.0

mA

02

---

12.5

03

---

11.0

Low level supply current

ICCL

VCC  = 5.5 V VIN  = 5.5 V

01

---

22.0

mA

02

---

16.0

03

---

16.0

Collector cut off current

ICEX

VCC  = 5.5 V, VIL  = GND VIH = 5.5 V

01, 02

---

250

µA

VCC  = 4.5 V, VIL  = GND VIH  = 5.5 V

03

---

250

µA

Propagation delay time, high to low level

tPHL

CL  = 50 pF ± 10%, RL  = 2800

01, 02

2.0

10.0

ns

03

2.0

13.0

Propagation delay time, low to high level

tPLH

CL  = 50 pF ± 10%, RL  = 2800

01, 02

2.0

9.0

ns

03

2.0

16.0