MIL-M-38510-303 Microcircuits, Digital, Bipolar, Low-Power Schottky Ttl, Nor Gates, Monolithic SiliconThis specification covers the detail requirements for monolithic silicon, low-power Schottky TTL, positive NOR logic gating microcircuits.

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Test

Symbol

Conditions  1/

-55°C = TC  = +125°C

0evice types

Limits

Unit

Min

Max

High level output voltage

VOH

VCC  = +4.5 V, VIN  = +0.7 V, IOH  = -400 ∝A

01, 02

+2.5

V

Low level output voltage

VOL

VCC  = +4.5 V, IOL  = +4 mA; VIN  = +2.0 V

All

+0.4

V

High level input current

IIH1

VCC  = +5.5 V, VIN  = +2.7 V

01, 02

+20

∝A

03

+40

IIH2

VCC  = +5.5 V, VIN  = +5.5 V

01, 02

+100

∝A

03

+200

Collector cut-off current

ICEX

VCC  = +4.5 V, VIN  = +0.7 V, VOH  = +5.5 V

03

+100

∝A

Low level input current

IIL

VCC  = +5.5 V, VIN  = +0.4 V

01

0

-400

∝A

02

-30

-400

03

-200

-760

Short circuit output current

IOS

VCC  = +5.5 V  2/, VIN  = 0 V

01, 02

-15

-130

mA

Input clamp voltage

VIC

VCC  = +4.5 V, IIN  = -18 mA, TC  = +25°C

All

-1.5

V

High level supply current

ICCH

VCC  = +5.5 V, VIN  = 0 V

01

+3.2

mA

02

+4.0

Low level supply current

ICCL

VCC  = +5.5 V, VIN  = +4.5 V

01

+5.4

mA

02

+6.8

Supply current

ICC

VCC  = +5.5 V  3/

03

+13

mA

Propagation delay time high-to-low level

tPHL

CL  = 50 pF ± 10%,

RL  = 2 kν ± 5%, VCC  = +5.0 V

01

2

30

ns

02

2

26

tPHL1

From A or B Other input low

CL  = 50 pF ± 10% RL  = 2 kν ± 5% VCC  = +5.0 V

03

2

45

tPHL2

From A or B Other input high

2

45

Propagation delay time low-to-high level

tPLH

CL  = 50 pF ± 10%

RL  = 2 kν ± 5%, VCC  = +5.0 V

01, 02

2

30

ns

tPLH1

From A or B Other input low

CL  = 50 pF ± 10% RL  = 2 kν ± 5% VCC  = +5.0 V

03

2

56

tPLH2

From A or B Other input high

2

56