MIL-M-38510/188
1.4 Recommended operating conditions.
Supply voltage ................................................................ +4.5 V dc minimum to +5.5 V dc maximum
Minimum high level input voltage ................................... +2.0 V dc
Maximum low level input voltage .................................... +0.8 V dc Normalized fanout (each output) 2/ ................................ 10 maximum Case operating temperature range (TC ) ......................... -55°C to 125°C Input setup time 3/
Data input ................................................................ 10 ns minimum
Write select 4/ ........................................................ 15 ns minimum
Input hold time 3/
Data input ................................................................ 15 ns minimum
Write select 4/ ........................................................ 5 ns minimum
Latch time for new data 5/ ............................................. 25 ns minimum
1.5 Description. The 16-bit TTL register file incorporates the equivalent of 98 gates on a monolithic chip measuring only 90 by 110 mils. The register file is organized as 4 words of 4 bits each and separate on-chip decoding is provided for addressing the four word locations to either write in or retrieve data. This permits simultaneous writing into one location and reading from another word location.
Four data inputs are available which are used to supply the 4-bit word to be stored. Location of the word is determined by the write address inputs A and 8 in conjunction with a write enable signal. Data applied at the inputs should be in its true form. That is, if a high level signal is desired from the output, a high level is applied at the data input for that particular bit location. The latch inputs are arranged so that new data will be accepted only if both internal address gate inputs are high. When this condition exists, data at the D input is transferred to the latch output. When the write enable input, GW, is high the data inputs are inhibited and their levels can cause no change in the information stored in the internal latches. When the read enable input, GR, is high the data outputs are inhibited and remain high.
The individual address lines permit direct acquisition of data stored in any four of the latches. Four individual decoding gates are used to complete the address for reading a word. When the read address is made in conjunction with the read enable signal, the word appears at the four outputs.
This arrangement (data entry addressing separate from data read addressing and individual sense line) eliminates recovery times, permits simultaneous reading and writing, and is limited in speed only by the write time (45 nanoseconds maximum) and the read time (35 nanoseconds maximum). The register file has a nondestructive readout in that data is not lost when addressed.
All inputs are buffered to lower the drive requirements to one normalized load, and input clamping diodes minimize switching transients to simplify system design. High speed, double ended AND-OR-INVERT gates are employed for the read address function and drive high sink current, open collector outputs. Up to 246 of these outputs may be wire-AND connected for increasing the capacity up to 1024 words. Any number of these registers may be paralleled to provide n-bit word length.
1/ Must withstand the added PD due to short circuit condition (e.g. IOS).
2/ Device will fanout in both high and low levels to the specified number of inputs of the same device type
as that being tested.
3/ With respect to write enable.
4/ Write select setup time will protect the data written into the previous address. If the protection of data in the previous address is not required, write select setup time can be ignored as any address
selection sustained for the final 30 ns of the write enable pulse and during the write select hold time will result in data being written with that location. Depending on the duration of the input conditions, one
of a number of previous addresses may have been written into.
5/ Latch time is the time required for the internal output of the latch to assume the state of the new data.
This is important only when attempting to read from a location immediately after that location has received new data.
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