MIL-M-38510-76 Microcircuits, Digital, Bipolar Schottky Ttl, Cascadable, Shift Registers, Monolithic SiliconThis specification covers the detail requirements for monolithic, silicon, Schottky TTL, shift register microcircuits. Two product assurance classes and a choice of case outlines and lead finishes are provided for each type and are reflected in the complete part number. For this product, the requirements of MIL-M-38510 have been superseded by MIL-PRF-38535, see 6.4.

Pages 1 - 2 - 3 - 4 - 5 - 6 - 7 - 8 - 9 - 10 - 11 - 12 - 13 - 14 - 15 - 16 - 17 - 18 - 19 - 20 - 21 - 22 - 23 - 24 - 25 - 26 - 27

MIL-M-3851O/76C

Device type O2

The register has two modes of operation:

Parallel (broadside) load

Shift (in the direction QA toward QD)

Parallel loading is accomplished by applying the four bits of data and taking the shift/load control input low.  The data is loaded into the associated flip-flop and appears at the outputs after the positive transition of the clock input.  During loading, serial data flow is inhibited.

Shifting is accomplished synchronously when the shift/load control input is high.  Serial data for this mode is entered at the J-K inputs.  These inputs permit the first stage to perform as a J-K, D, or T-type flip-flop as shown in the truth table.

H = high level (steady state) L = low level (steady state)

x = irrelevant (any input, including transitions)

t  = transition from low to high level

a, b, c, d, = the level of steady state input at inputs A, B, C, or D, respectively.

QAO, QBO, QCO, QDO = the level of QA, QB, QC, or QD, respectively, before the indicated steady state input conditions were established.

QAn, QBn, QCn = the level of QA, QB, or QC, respectively, before the most recent transition of the clock.

Figure 2.  Truth tables and timing diagrams - Continued.

1O