MIL-M-38510-19 Microcircuits, Digital Ttl, Parity Generators/Checkers, Monolithic SiliconThis specification covers the detail requirements for monolithic, silicon, TTL, parity generators/checkers. Two product assurance classes and a choice of case outlines and lead finishes are provided for each type and are reflected in the complete part number. For this product, the requirements of MIL-M-38510 have been superseded by MIL-PRF-38535, see 6.4.

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Test

Symbol

Conditions

-55°C ≤ TC  ≤ +125°C

unless otherwise specified

Test limits

Min

Max

Unit

High level output voltage

VOH

VCC  = 4.5 V, VIH  = 2.0 V VIL  = 0.8 V, IOH = -800 µA

2.4

---

V

Low level output voltage

VOL

VCC  = 4.5 V, VIH  = 2.0 V VIL  = 0.8 V, IOL = 16 mA

---

0.4

V

Input clamp voltage

VIC

VCC  = 4.5 V, IIN  = -12 mA TC = 25°C

---

-1.5

V

High level input current

IIH1

VCC  = 5.5 V, VIN  = 2.4 V

---

40

µA

High level input current

(EVEN IN and ODD IN)

IIH2

VCC  = 5.5 V, VIN  = 2.4 V

---

80

µA

High level input current

IIH3

VCC  = 5.5 V, VIN  = 5.5 V

---

100

µA

High level input current

(EVEN IN and ODD IN)

IIH4

VCC  = 5.5 V, VIN  = 5.5 V

---

200

µA

Low level input current

IIL1

VCC  = 5.5 V, VIN  = 0.4 V

-0.7

-1.6

mA

Low level input current

(EVEN IN and ODD IN)

IIL2

VCC  = 5.5 V, VIN  = 0.4 V

-0.7

-3.2

mA

Short circuit output current

IOS

VCC  = 5.5 V  1/

-20

-55

mA

Supply current

ICC

VCC  = 5.5 V,

VODD  = VEVEN  = 2.4 V

---

49

mA

Propagation delay to high logic level

(data to L EVEN, EVEN IN grounded)

tPLH1

CL  = 50 pF, RL = 400 0

2

67

ns

Propagation delay to low logic level

(data to L EVEN, EVEN IN grounded)

tPHL1

2

54

ns

Propagation delay to high logic level

(data to L EVEN, ODD IN grounded)

tPLH2

2

83

ns

Propagation delay to low logic level

(data to L EVEN, ODD IN grounded)

tPHL2

2

96

ns

Propagation delay to high logic level

(data to L ODD, ODD IN grounded)

tPLH3

2

67

ns

Propagation delay to low logic level

(data to L ODD, ODD IN grounded)

tPHL3

2

54

ns

Propagation delay to high logic level

(data to L ODD, EVEN IN grounded)

tPLH4

2

83

ns

Propagation delay to low logic level

(data to L ODD, EVEN IN grounded)

tPHL4

2

93

ns

Propagation delay to high logic level

(EVEN or ODD to L EVEN or

L ODD)

tPLH5

2

31

ns

Propagation delay to low logic level

(EVEN or ODD to L EVEN or

L ODD)

tPHL5

2

19

ns